View SST25VF016B_8640133.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

? 2015 microchip technology inc. ds20005044c-page 1 features single voltage read and write operations - 2.7-3.6v serial interface architecture - spi compatible: mode 0 and mode 3 high speed clock frequency - up to 50 mhz superior reliability - endurance: 100,000 cycles (typical) - greater than 100 years data retention low power consumption: - active read current: 10 ma (typical) - standby current: 5 a (typical) flexible erase capability - uniform 4 kbyte sectors - uniform 32 kbyte overlay blocks - uniform 64 kbyte overlay blocks fast erase and byte-program: - chip-erase time: 35 ms (typical) - sector-/block-erase time: 18 ms (typical) - byte-program time: 7 s (typical) auto address increment (aai) programming - decrease total chip programming time over byte-program operations end-of-write detection - software polling the busy bit in status register - busy status readout on so pin in aai mode hold pin (hold#) - suspends a serial sequence to the memory without deselecting the device write protection (wp#) - enables/disables the lock-down function of the status register software write protection - write protection through block-protection bits in status register temperature range - commercial: 0c to +70c - industrial: -40c to +85c packages available - 8-lead soic (200 mils) - 8-contact wson (6mm x 5mm) all devices are rohs compliant product description the 25 series serial flash family features a four-wire, spi-compatible interface that allows for a low pin-count package which occupies less board space and ulti- mately lowers total system costs. the SST25VF016B devices are enhanced with improved operating fre- quency and even lower power consumption than the original sst25vfxxxa devices. SST25VF016B spi serial flash memories are manufactured with propri- etary, high-performance cmos superflash technol- ogy. the split-gate cell design and thick-oxide tunneling injector attain better re liability and manufacturability compared with alternate approaches. SST25VF016B devices significantly improve perfor- mance and reliability, while lowering power consump- tion. the devices write (progr am or erase) with a single power supply of 2.7-3.6v for SST25VF016B. the total energy consumed is a function of the applied voltage, current, and time of application. since for any given voltage range, the superflash technology uses less current to program and has a shorter erase time, the total energy consumed during any erase or program operation is less than altern ative flash memory technol- ogies. the SST25VF016B device is offered in both 8-lead soic (200 mils) and 8-contact wson (6mm x 5mm) packages. see figure 2-1 for pin assignments. SST25VF016B 16 mbit spi serial flash downloaded from: http:///
SST25VF016B ds20005044c-page 2 ? 2015 microchip technology inc. to our valued customers it is our intention to provide our valued customers with the bes t documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments rega rding this publication, please contact the marketing communications department via e- mail at docerrors@microchip.com . we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data sheet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining it s literature number found on the bottom outside corner of any page. the last character of the literature number is the version number, (e.g., ds30000000a is version a of document ds30000000). errata an errata sheet, describing minor operati onal differences from the data sheet and re commended workarounds, may exist for curren t devices. as device/documentation i ssues become known to us, we will publish an errata sheet. the errata will specify the revisi on of silicon and revision of document to which it applies. to determine if an errata sheet exists for a partic ular device, pleas e check with one of the following: microchips worldwide web site; http://www.microchip.com your local microchip sales office (see last page) when contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. customer notification system register on our web site at www.microchip.com to receive the most current information on all of our products. downloaded from: http:///
? 2015 microchip technology inc. ds20005044c-page 3 SST25VF016B 1.0 block diagram figure 1-1: functional block diagram 1271 b1.0 i/o buffers and data latches superflash memory x - decoder control logic address buffers and latches ce# y - decoder sck si so wp# hold# serial interface downloaded from: http:///
SST25VF016B ds20005044c-page 4 ? 2015 microchip technology inc. 2.0 pin description figure 2-1: pin assignments table 2-1: pin description symbol pin name functions sck serial clock to provide the timing of the serial interface. commands, addresses, or input data are latched on the rising edge of the clock input, while output data is shifted out on the falling edge of the clock input. si serial data input to transfer commands, ad dresses, or data serially into the device. inputs are latched on the rising edge of the serial clock. so serial data output to transfer data serially out of the device. data is shifted out on the falling edge of the serial clock. outputs flash busy status during aai programming when reconfigured as ry/by# pin. see hardware end-of-write detection on page 11 for details. ce# chip enable the device is enabled by a high to low transition on ce#. ce# must remain low for the duration of any command sequence. wp# write protect the write protect (wp#) pin is used to enable/disable bpl bit in the status register. hold# hold to temporarily stop serial communicat ion with spi flash memory without resetting the device. v dd power supply to provide power supply voltage: 2.7-3.6v for SST25VF016B v ss ground 12 3 4 87 6 5 ce# so wp# v ss v dd hold#sck si top view 1271 08-soic s2a p1.0 12 3 4 87 6 5 ce# so wp# v ss top view v dd hold#sck si 1271 08-wson qa p2.0 8-lead soic 8-contact wson downloaded from: http:///
? 2015 microchip technology inc. ds20005044c-page 5 SST25VF016B 3.0 memory organization the SST25VF016B superflash memory array is orga- nized in uniform 4 kbyte erasable sectors with 32 kbyte overlay blocks and 64 kbyte overlay eras- able blocks. 4.0 device operation the SST25VF016B is accessed through the spi (serial peripheral interface) bus compatible protocol. the spi bus consist of four control lines; chip enable (ce#) is used to select the device, and data is accessed through the serial data input (si), se rial data output (so), and serial clock (sck). the SST25VF016B supports both mode 0 (0,0) and mode 3 (1,1) of spi bus operations. the difference between the two modes, as shown in figure 4-1 , is the state of the sck signal when the bus master is in stand-by mode and no data is being transferred. the sck signal is low for mode 0 and sck signal is high for mode 3. for both modes, the serial data in (si) is sam- pled at the rising edge of the sck clock signal and the serial data output (so) is driven after the falling edge of the sck clock signal. figure 4-1: spi protocol 4.1 hold operation the hold# pin is used to pause a serial sequence underway with the spi flash memory without resetting the clocking sequence. to activate the hold# mode, ce# must be in active low state. the hold# mode begins when the sck active low state coincides with the falling edge of the hold# signal. the hold mode ends when the hold# signals rising edge coincides with the sck active low state. if the falling edge of the hold# signal does not coin- cide with the sck active low state, then the device enters hold mode when the sck next reaches the active low state. similarly, if the rising edge of the hold# signal does not coincide with the sck active low state, then the device exits in hold mode when the sck next reaches the active low state. see figure 4-2 for hold condition waveform. once the device enters hold mode, so will be in high- impedance state while si and sck can be v il or v ih. if ce# is driven active high during a hold condition, it resets the internal logic of the device. as long as hold# signal is low, the memory remains in the hold condition. to resume communication with the device, hold# must be driven active high, and ce# must be driven active low. see figure 5-3 for hold timing. figure 4-2: hold condition waveform 4.2 write protection SST25VF016B provides software write protection. the write protect pin (wp#) enables or disables the lock- down function of the status register. the block-protec- tion bits (bp3, bp2, bp1, bp0, and bpl) in the status register provide write protection to the memory array and the status register. see table 4-3 for the block-pro- tection description. 1271 spiprot.0 mode 3 sck si so ce# mode 3 don't care bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mode 0 mode 0 high impedance msb msb active hold active hold active 1271 holdcond.0 sck hold# downloaded from: http:///
SST25VF016B ds20005044c-page 6 ? 2015 microchip technology inc. 4.2.1 write protect pin (wp#) the write protect (wp#) pin enables the lock-down function of the bpl bit (bit 7) in the status register. when wp# is driven low, the execution of the write- status-register (wrsr) instruction is determined by the value of the bpl bit (see table 4-1 ). when wp# is high, the lock-down function of the bpl bit is disabled. 4.3 status register the software status register provides status on whether the flash memory array is available for any read or write operation, w hether the device is write enabled, and the state of t he memory write protection. during an internal erase or program operation, the sta- tus register may be read only to determine the comple- tion of an operation in progress. table 4-2 describes the function of each bit in t he software status register. 4.3.1 busy the busy bit determines whether there is an internal erase or program operation in progress. a 1 for the busy bit indicates the device is busy with an operation in progress. a 0 indicates the device is ready for the next valid operation. 4.3.2 write enable latch (wel) the write-enable-latch (wel) bit indicates the status of the internal memory writ e enable latch. if the write- enable-latch bit is set to 1 , it indicates the device is write enabled. if the bit is set to 0 (reset), it indicates the device is not write enabled and does not accept any memory write (program/erase) commands. the write-enable-latch bit is automatically reset under the following conditions: power-up write-disable (wrdi) instruction completion byte-program inst ruction completion auto address increment (aai) programming is completed or reached its highest unprotected memory address sector-erase inst ruction completion block-erase instruction completion chip-erase instruction completion write-status-register instructions 4.3.3 auto address increment (aai) the auto address increment programming-status bit provides status on whether the device is in auto address increment (aai) programming mode or byte- program mode. the default at power up is byte-pro- gram mode. table 4-1: conditions to execute write- status-register (wrsr) instruction wp# bpl execute wrsr instruction l1 not allowed l0 allowed hx allowed table 4-2: software status register bit name function default at power-up read/write 0 busy 1 = internal write operation is in progress 0 = no internal write operation is in progress 0r 1 wel 1 = device is memory write enabled 0 = device is not memory write enabled 0r 2 bp0 indicate current level of block write protection (see table 4-3 ) 1r / w 3 bp1 indicate current level of block write protection (see table 4-3 ) 1r / w 4 bp2 indicate current level of block write protection (see table 4-3 ) 1r / w 5 bp3 indicate current level of block write protection (see table 4-3 ) 0r / w 6 aai auto address increment programming status 1 = aai programming mode 0 = byte-program mode 0r 7 bpl 1 = bp3, bp2, bp1, bp0 are read-only bits 0 = bp3, bp2, bp1, bp0 are read/writable 0r / w downloaded from: http:///
? 2015 microchip technology inc. ds20005044c-page 7 SST25VF016B 4.3.4 block protection (bp3,bp2, bp1, bp0) the block-protection (bp3 , bp2, bp1, bp0) bits define the size of the memory area, as defined in table 4-3 , to be software protected against any memory write (pro- gram or erase) operation. the write-status-register (wrsr) instruction is used to program the bp3, bp2, bp1 and bp0 bits as long as wp# is high or the block- protect-lock (bpl) bit is 0. chip-erase can only be executed if block-protection bits are all 0. after power- up, bp3, bp2, bp1 and bp0 are set to 1. 4.3.5 block protection lock-down (bpl) wp# pin driven low (v il ), enables the block-protection- lock-down (bpl) bit. when bpl is set to 1, it prevents any further alteration of the bpl, bp3, bp2, bp1, and bp0 bits. when the wp# pin is driven high (v ih ), the bpl bit has no effect and its value is dont care. after power-up, the bpl bit is reset to 0. table 4-3: software status register block protection for SST25VF016B 1 1. x = don?t care (reser v ed) defa u lt is ?0 protection level status register bit 2 2. defa u lt at po w er- u p for bp2, bp1, and bp0 is ? 111?. (all blocks protected) protected memory address bp3 bp2 bp1 bp0 16 mbit n one x 0 0 0 n one upper 1/32 x 0 0 1 1f0000h-1fffffh upper 1/16 x 0 1 0 1e0000h-1fffffh upper 1/ 8 x 0 1 1 1c0000h-1fffffh upper 1/4 x 1 0 0 1 8 0000h-1fffffh upper 1/2 x 1 0 1 100000h-1fffffh all blocks x 1 1 0 000000h-1fffffh all blocks x 1 1 1 000000h-1fffffh downloaded from: http:///
SST25VF016B ds20005044c-page 8 ? 2015 microchip technology inc. 4.4 instructions instructions are used to read, write (erase and pro- gram), and configure the SST25VF016B. the instruc- tion bus cycles are 8 bits each for commands (op code), data, and addresses. prior to executing any byte-program, auto address increment (aai) program- ming, sector-erase, block-erase, write-status-regis- ter, or chip-erase instructions, the write-enable (wren) instruction must be executed first. the com- plete list of instructions is provided in table 4-4 . all instructions are synchronized off a high to low transition of ce#. inputs will be accepted on the rising edge of sck starting with the most si gnificant bit. ce# must be driven low before an instruction is entered and must be driven high after the last bit of the instruction has been shifted in (except for read, read-id, and read-status- register instructions). any low to high transition on ce#, before receiving the last bit of an instruction bus cycle, will terminate the instruction in progress and return the device to standby mode. instruction com- mands (op code), addresses, and data are all input from the most significant bit (msb) first. table 4-4: device operation instructions instruction description op code cycle 1 1. one b u s cycle is eight clock periods. address cycle(s) 2 2. address bits above the most si gnificant bit of each density can be v il or v ih . dummy cycle(s) data cycle(s) maximum frequency read read memory at 25 mhz 0000 0011b (03h) 301 t o ? 25 mhz high-speed read read memory at 50 mhz 0000 1011b (0bh) 311 t o ? 50 mhz 4 kbyte sector- erase 3 3. 4kbyte sector erase addresses: u se a ms -a 12, remaining addresses are don?t care b u t m u st be set either at v il or v ih. erase 4 kbyte of memory array 0010 0000b (20h) 3005 0 m h z 32 kbyte block- erase 4 4. 32kbyte block erase addresses: u se a ms -a 15, remaining addresses are don?t care b u t m u st be set either at v il or v ih. erase 32 kbyte block of memory array 0101 0010b (52h) 3005 0 m h z 64 kbyte block- erase 5 5. 64kbyte block erase addresses: u se a ms -a 16, remaining addresses are don?t care b u t m u st be set either at v il or v ih. erase 64 kbyte block of memory array 1101 1000b (d8h) 3005 0 m h z chip-erase erase full memory array 0110 0000b (60h) or 1100 0111b (c7h) 0005 0 m h z byte-program to program one data byte 0000 0010b (02h) 3015 0 m h z aai-word-pro- gram 6 6. to contin u e programming to the next seq u ential address location, enter the 8 -bit command, adh, follo w ed by 2 bytes of data to be programmed. data byte 0 w ill be programmed into the initial address [a 23 -a 1 ] w ith a 0 =0, data byte 1 w ill be pro- grammed into the initial address [a 23 -a 1 ] w ith a 0 =1. auto address increment programming 1010 1101b (adh) 302 t o ? 50 mhz rdsr 7 7. the read-stat u s-register is contin u o u s w ith ongoing clock cycles u ntil terminated by a lo w to high transition on ce#. read-status-register 0000 0101b (05h) 001 t o ? 50 mhz ewsr enable-write-status-register 0101b 0000b (50h) 0005 0 m h z wrsr write-status-register 0000 0001b (01h) 0015 0 m h z wren write-enable 0000 0110b (06h) 0005 0 m h z wrdi write-disable 0000 0100b (04h) 0005 0 m h z rdid 8 8 .man u fact u rer?s id is read w ith a 0 =0, and device id is read w ith a 0 =1. all other address bits are 00h. the man u fact u rer?s id and device id o u tp u t stream is contin u o u s u ntil terminated by a lo w -to-high transition on ce#. read-id 1 001 0000b (90h) or 1010 1011b (abh) 301 t o ? 50 mhz jedec-id jedec id read 1001 1111b (9fh) 003 t o ? 50 mhz ebsy enable so to output ry/by# status during aai program- ming 0111 0000b (70h) 0005 0 m h z dbsy disable so as ry/by# status during aai program- ming 1000 0000b (80h) 0005 0 m h z downloaded from: http:///
? 2015 microchip technology inc. ds20005044c-page 9 SST25VF016B 4.4.1 read (25 mhz) the read instruction, 03h, supports up to 25 mhz read. the device outputs the data starting from the specified address location. the data output stream is continuous through all addresses until terminated by a low to high transition on ce#. the internal address pointer will automatically increment until the highest memory address is reached. once the highest memory address is reached, the address pointer will automati- cally increment to the beginning (wrap-around) of the address space. once the data from address location 1fffffh has been read, the next output will be from address location 000000h. the read instruction is initiated by executing an 8-bit command, 03h, followed by address bits [a 23 -a 0 ]. ce# must remain active low for the duration of the read cycle. see figure 4-3 for the read sequence. figure 4-3: read sequence 4.4.2 high-speed-read (50 mhz) the high-speed-read instruction supporting up to 50 mhz read is initiated by executing an 8-bit command, 0bh, followed by address bits [a 23 -a 0 ] and a dummy byte. ce# must remain active low for the duration of the high-speed-read cycle. see figure 4-4 for the high- speed-read sequence. following a dummy cycle, the high-speed-read instruction outputs the data starting from the specified address location. the data output stream is continuous through all addresses until terminated by a low to high transition on ce#. the internal address pointer will automatically increment until the highest memory address is reached. once the highest memory address is reached, the address pointer will automatically incre- ment to the beginning (wr ap-around) of the address space. once the data from address location 1fffffh has been read, the next output will be from address location 000000h. figure 4-4: high-speed-read sequence 1271 readse q .0 ce# so si sck add. 012345678 add. add. 03 high impedance 15 16 23 24 31 32 39 40 70 47 48 55 56 63 64 n+2 n+3 n+4 n n+1 d out msb msb msb mode 0 mode 3 d out d out d out d out 1271 hsrdseq.0 ce# so si sck add. 01234567 8 add. add. 0b high impeda n ce 15 16 23 24 31 32 39 40 47 4 8 55 56 63 64 n +2 n +3 n +4 n n +1 x msb msb msb mode 0 mode 3 d out d out d out d out 8 0 71 72 d out n ote: x = d u mmy byte: 8 clocks inp u t d u mmy cycle ( v il or v ih ) downloaded from: http:///
SST25VF016B ds20005044c-page 10 ? 2015 microchip technology inc. 4.4.3 byte-program the byte-program instruction programs the bits in the selected byte to the desired data. the selected byte must be in the erased state (ffh) when initiating a pro- gram operation. a byte-program instruction applied to a protected memory area will be ignored. prior to any write operation, the write-enable (wren) instruction must be execut ed. ce# must remain active low for the duration of the byte-program instruction. the byte-program instruction is initiated by executing an 8-bit command, 02h, followed by address bits [a 23 - a 0 ]. following the address, the data is input in order from msb (bit 7) to lsb (bit 0). ce# must be driven high before the instruction is executed. the user may poll the busy bit in the software status register or wait t bp for the completion of the internal self-timed byte- program operation. see figure 4-5 for the byte-pro- gram sequence. figure 4-5: byte-program sequence 4.4.4 auto address increment (aai) word-program the aai program instruction allows multiple bytes of data to be programmed without re-issuing the next sequential address location. this feature decreases total programming time when multiple bytes or entire memory array is to be progr ammed. an aai word pro- gram instruction pointing to a protected memory area will be ignored. the selected address range must be in the erased state (ffh) when initiating an aai word program operation. while within aai word program- ming sequence, only the following instructions are valid: for software end-of -write detectionaai word (adh), wrdi (04h), and rdsr (05h); for hardware end-of-write detectionaai word (adh) and wrdi (04h). there are three options to determine the com- pletion of each aai word program cycle: hardware detection by reading the serial output, software detec- tion by polling the busy bit in the software status reg- ister, or wait t bp. refer toend-of-write detection for details. prior to any write operation, the write-enable (wren) instruction must be executed. initiate the aai word program instruction by executing an 8-bit command, adh, followed by address bits [a 23 -a 0 ]. following the addresses, two bytes of data are input sequentially, each one from msb (bit 7) to lsb (bit 0). the first byte of data (d0) is programmed into the initial address [a 23 - a 1 ] with a 0 =0, the second byte of data (d1) is pro- grammed into the initial address [a 23 -a 1 ] with a 0 =1. ce# must be driven high before executing the aai word program instruction. check the busy status before entering the next valid command. once the device indicates it is no longer busy, data for the next two sequential addresses may be programmed, fol- lowed by the next two, and so on. when programming the last desired word, or the high- est unprotected memory address, check the busy sta- tus using either the hardware or software (rdsr instruction) method to check for program completion. once programming is complete, use the applicable method to terminate aai. if the device is in software end-of-write detection mode, execute the write-dis- able (wrdi) instruction, 04h. if the device is in aai hardware end-of-write detection mode, execute the write-disable (wrdi) instruction, 04h, followed by the 8-bit dbsy command, 80h. there is no wrap mode during aai programming once the highest unprotected memory address is reached. see figures 4-8 and 4-9 for the aai word programming sequence. 4.4.5 end-of-write detection there are three methods to determine completion of a program cycle during aai word programming: hard- ware detection by reading the serial output, software detection by polling the busy bit in the software status register, or wait t bp. the hardware end-of-write detection method is described in the section below. 1271 byteprog.0 ce# so si sck add. 012345678 add. add. d in 02 high impedance 15 16 23 24 31 32 39 mode 0 mode 3 msb msb msb lsb downloaded from: http:///
? 2015 microchip technology inc. ds20005044c-page 11 SST25VF016B 4.4.6 hardware end-of-write detection the hardware end-of-write detection method elimi- nates the overhead of polling the busy bit in the soft- ware status register during an aai word program operation. the 8-bit command, 70h, configures the serial output (so) pin to indicate flash busy status during aai word programming. (see figure 4-6 ) the 8- bit command, 70h, must be executed prior to initiating an aai word-program instruction. once an internal programming operation begins, asserting ce# will immediately drive the status of the internal flash status on the so pin. a 0 indicates the device is busy and a 1 indicates the device is r eady for the next instruction. de-asserting ce# will return the so pin to tri-state. while in aai and hardware end-of-write detection mode, the only valid instructions are aai word (adh) and wrdi (04h). to exit aai hardware end-of-write detection, first exe- cute wrdi instruction, 04h, to reset the write-enable- latch bit (wel=0) and aai bit. then execute the 8-bit dbsy command, 80h, to disabl e ry/by# status during the aai command. see figures 4-7 and 4-8 . figure 4-6: enable so as hardware ry/by# during aai programming figure 4-7: disable so as hardware ry/by# during aai programming ce# so si sck 01234567 70 high impedance mode 0 mode 3 1271 ena b leso.0 msb ce# so si sck 01234567 8 0 high impeda n ce mode 0 mode 3 1271 disableso.0 msb downloaded from: http:///
SST25VF016B ds20005044c-page 12 ? 2015 microchip technology inc. figure 4-8: auto address increment ( aai) word-program sequence with hardware end-of-write detection figure 4-9: auto address increment ( aai) word-program sequence with software end-of-write detection ce# si sck so 1271 aai.hw.3 check for flash busy status to load next v alid 1 command load aai command, address, 2 b ytes data note: 1. valid commands during aai programming: aai command or wrdi command 2. user must configure the so pin to output flash busy status during aai programming 0 aaa ad d0 ad mode 3mode 0 d1 d2 d3 7 wren ebsy 0 7 078 32 47 15 16 23 24 31 0 40 39 7 8 15 16 23 d out wrdi followed b y dbsy to exit aai mode wrdi rdsr 70 1 5 78 0 dbsy 7 0 ce# cont. si cont. sck cont. so cont. last 2 data bytes ad d n-1 d n 7 8 15 16 23 0 check for flash busy status to load next v alid 1 command 07 8 32 47 15 16 23 24 31 0 40 39 7 8 15 16 23 7 8 15 16 23 70 1 5 7 8 00 ce# si sck so d out mode 3mode 0 1271 aai.s w .1 n ote: 1. v alid commands d u ring aai programming: aai command, rdsr command, or w rdi command w ait t bp or poll soft w are stat u s register to load next valid 1 command last 2 data bytes w rdi to exit aai mode load aai command, address, 2 bytes data aaa ad d0 ad d1 d2 d3 ad d n-1 d n w rdi rdsr downloaded from: http:///
? 2015 microchip technology inc. ds20005044c-page 13 SST25VF016B 4.4.7 4-kbyte sector-erase the sector-erase instructio n clears all bits in the selected 4 kbyte sector to ffh. a sector-erase instruction applied to a protected memory area will be ignored. prior to any write operation, the write-enable (wren) instruction must be executed. ce# must remain active low for the duration of any command sequence. the sector-erase instruction is initiated by executing an 8-bit command, 20h, followed by address bits [a 23 -a 0 ]. address bits [a ms -a 12 ] (a ms =most sig- nificant address) are us ed to determine the sector address (sa x ), remaining address bits can be v il or v ih. ce# must be driven high before the instruction is exe- cuted. the user may poll the busy bit in the software status register or wait t se for the completion of the internal self-timed se ctor-erase cycle. see figure 4-10 for the sector-erase sequence. figure 4-10: sector-erase sequence 4.4.8 32-kbyte and 64-kbyte block- erase the 32-kbyte block-erase instruction clears all bits in the selected 32 kbyte bl ock to ffh. a block-erase instruction applied to a protected memory area will be ignored. the 64-kbyte block-erase instruction clears all bits in the selected 64 kbyte bl ock to ffh. a block-erase instruction applied to a pr otected memory area will be ignored. prior to any writ e operation, the write-enable (wren) instruction must be executed. ce# must remain active low for the duration of any command sequence. the 32-kbyte block-erase in struction is initiated by executing an 8-bit command, 52h, followed by address bits [a 23 -a 0 ]. address bits [a ms -a 15 ] (a ms = most sig- nificant address) are used to determine block address (ba x ), remaining address bits can be v il or v ih. ce# must be driven high before th e instruction is executed. the 64-kbyte block-erase instructi on is initiated by executing an 8-bit command d8h, followed by address bits [a 23 -a 0 ]. address bits [a ms -a 15 ] are used to determine block address (ba x ), remaining address bits can be v il or v ih. ce# must be driven high before the inst ruction is executed. the user may poll the busy bit in the software status register or wait t be for the completion of the internal self-timed 32- kbyte block-erase or 64-kbyte block-erase cycles. see figures 4-11 and 4-12 for the 32-kbyte block- erase and 64-kbyte block-erase sequences. figure 4-11: 32-kbyte block-erase sequence ce# so si sck add. 012345678 add. add. 20 high impedance 15 16 23 24 31 mode 0 mode 3 1271 secerase.0 msb msb ce# so si sck addr 01234567 8 addr addr 52 high impeda n ce 15 16 23 24 31 mode 0 mode 3 1271 32kbkler.0 msb msb downloaded from: http:///
SST25VF016B ds20005044c-page 14 ? 2015 microchip technology inc. figure 4-12: 64-kbyte block-erase sequence 4.4.9 chip-erase the chip-erase instruction clears all bits in the device to ffh. a chip-erase instruction will be ignored if any of the memory area is protected. prior to any write oper- ation, the write-enable (wren) instruction must be exe- cuted. ce# must remain active low for the duration of the chip-erase instruction sequence. the chip-erase instruction is initiated by executing an 8-bit command, 60h or c7h. ce# must be driven high before the instruction is executed. the user may poll the busy bit in the software status register or wait t ce for the completion of the internal self-timed chip-erase cycle. see figure 4-13 for the chip-erase sequence. figure 4-13: chip-erase sequence ce# so si sck addr 012345678 addr addr d8 high impedance 15 16 23 24 31 mode 0 mode 3 1271 63kblker.0 msb msb ce# so si sck 01234567 60 or c7 high impeda n ce mode 0 mode 3 1271 cher.0 msb downloaded from: http:///
? 2015 microchip technology inc. ds20005044c-page 15 SST25VF016B 4.4.10 read-status-register (rdsr) the read-status-register (rdsr) instruction allows reading of the status regist er. the status register may be read at any time even during a write (program/ erase) operation. when a write operation is in prog- ress, the busy bit may be checked before sending any new commands to assure that the new commands are properly received by the device. ce# must be driven low before the rdsr instruction is entered and remain low until the status data is read. read-status-register is continuous with ongoing clock cycles until it is termi- nated by a low to high transition of the ce#. see figure 4-14 for the rdsr instruction sequence. figure 4-14: read-status-register (rdsr) sequence 4.4.11 write-enable (wren) the write-enable (wren) in struction sets the write- enable-latch bit in the status register to 1 allowing write operations to occur. the wren instruction must be executed prior to any write (program/erase) opera- tion. the wren instruction may also be used to allow execution of the write-status-register (wrsr) instruc- tion; however, the write-enable-latch bit in the status register will be cleared upon the rising edge ce# of the wrsr instruction. ce# must be driven high before the wren instruction is executed. figure 4-15: write en able (wren) sequence 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1271 rdsrse q .0 mode 3 sck si so ce# bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 05 mode 0 high impedance status register out msb msb ce# so si sck 01234567 06 high impeda n ce mode 0 mode 3 1271 w re n .0 msb downloaded from: http:///
SST25VF016B ds20005044c-page 16 ? 2015 microchip technology inc. 4.4.12 write-disable (wrdi) the write-disable (wrdi) inst ruction resets the write- enable-latch bit and aai bit to 0 disabling any new write operations from occurring. the wrdi instruction will not terminate any programming operation in progress. any program operation in progress may continue up to t bp after executing the wrdi inst ruction. ce# must be driven high before the wrdi inst ruction is executed. figure 4-16: write di sable (wrdi) sequence 4.4.13 enable-write-status- register (ewsr) the enable-write-status-regi ster (ewsr) instruction arms the write-status-register (wrsr) instruction and opens the status register for alteration. the write- status-register instruction must be executed immedi- ately after the execution of the enable-write-status- register instruction. this two-step instruction sequence of the ewsr instruction followed by the wrsr instruction works like sdp (software data pro- tection) command structur e which prevents any acci- dental alteration of the status register values. ce# must be driven low before the ewsr instruction is entered and must be driven high bef ore the ewsr instruction is executed. 4.4.14 write-status-register (wrsr) the write-status-register in struction writes new val- ues to the bp3, bp2, bp1, bp0, and bpl bits of the sta- tus register. ce# must be driven low before the command sequence of the wrsr instruction is entered and driven high before the wrsr instruction is executed. see figure 4-17 for ewsr or wren and wrsr instruction sequences. executing the write-status-r egister instruction will be ignored when wp# is low and bpl bit is set to 1. when the wp# is low, the bpl bit can only be set from 0 to 1 to lock-down the status register, but cannot be reset from 1 to 0. when wp# is high, the lock-down function of the bpl bit is disabled and the bpl, bp0, and bp1 and bp2 bits in the status register can all be changed. as long as bpl bit is set to 0 or wp# pin is driven high (v ih ) prior to the low-to-high transition of the ce# pin at the end of the wrsr instruction, the bits in the status register can all be altered by the wrsr instruction. in this case, a single wrsr in struction can set the bpl bit to 1 to lock down the status register as well as altering the bp0, bp1, and bp2 bits at the same time. see table 4-1 for a summary description of wp# and bpl functions. figure 4-17: enable-write-st atus-register (ewsr) or write-enable (wren) and write-status-register (wrsr) sequence ce# so si sck 01234567 04 high impedance mode 0 mode 3 1271 wrdi.0 msb 1271 e w sr.0 mode 3 high impeda n ce mode 0 status register i n 76543210 msb msb msb 01 mode 3 sck si so ce# mode 0 50 or 06 01234567 01234567 8 9 101112131415 downloaded from: http:///
? 2015 microchip technology inc. ds20005044c-page 17 SST25VF016B 4.4.15 jedec read-id the jedec read-id instruction identifies the device as SST25VF016B and the manufacturer as microchip. the device information can be read from executing the 8-bit command, 9fh. following the jedec read-id instruction, the 8-bit manufacturers id, bfh, is output from the device. after that, a 16-bit device id is shifted out on the so pin. byte 1, bfh, identifies the manufac- turer as microchip. byte 2, 25h, identifies the memory type as spi serial flash. byte 3, 41h, identifies the device as SST25VF016B. the instruction sequence is shown in figure 4-18 . the jedec read id instruction is terminated by a low to high transition on ce# at any time during data output. if no other command is issued after executing the jedec read-id instruction, issue a 00h (nop) command before going into standby mode (ce#=v ih ). figure 4-18: jedec read-id sequence table 4-5: jedec read-id data manufacturer?s id device id memory type memory capacity byte1 byte 2 byte 3 bfh 25h 41h 25 41 1271 jedecid.1 ce# so si sck 012345678 high impedance 15 16 14 28 29 30 31 bf mode 3mode 0 msb msb 9 10111213 1718 32 34 9f 19 20 21 22 23 33 24 25 26 27 downloaded from: http:///
SST25VF016B ds20005044c-page 18 ? 2015 microchip technology inc. 4.4.16 read-id (rdid) the read-id instruction (rdid) identifies the devices as SST25VF016B and manufacturer as microchip. this command is backward compatible to all sst25xfxxxa devices and should be used as default device identifi- cation when multiple versions of spi serial flash devices are used in a design. the device information can be read from executing an 8-bit command, 90h or abh, followed by address bits [a 23 -a 0 ]. following the read-id instruction, the manufacturers id is located in address 00000h and the device id is located in address 00001h. once the device is in read-id mode, the manufacturers and devi ce id output data toggles between address 00000h and 00001h until terminated by a low to high transition on ce#. refer to tables 4-5 and 4-6 for device identification data. figure 4-19: read-id sequence table 4-6: product identification address data manufacturers id 00000h bfh device id sst25 v f016b 00001h 41h 1271 rdid.0 ce# so si sck 00 012345678 00 add 1 90 or ab high impedance 15 16 23 24 31 32 39 40 47 48 55 56 63 bf de v ice id bf de v ice id note: the manufacturer's and de v ice id output stream is continuous until terminated b y a low to high transition on ce#. de v ice id = 41h for SST25VF016B 1. 00h will output the manfacturer's id first and 01h will output de v ice id first b efore toggling b etween the two. high impedance mode 3mode 0 msb msb msb downloaded from: http:///
? 2015 microchip technology inc. ds20005044c-page 19 SST25VF016B 5.0 electrical specifications absolute maximum stress ratings (applied conditions greater than those listed u nder ?absol u te maxi- m u m stress ratings? may ca u se permanent damage to the device. this is a stress rating only and f u nc- tional operation of the device at these conditions or conditions greater than thos e defined in the operational sections of this data sheet is not implied. expos u re to absol u te maxim u m stress rating conditions may affect device reliability.) te m p e r a t u re under bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55c to +125c storage temperat u re . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65c to +150c d. c. v oltage on any pin to gro u nd potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 v to v dd +0.5 v transient v oltage (<20 ns) on any pin to gro u nd potential . . . . . . . . . . . . . . . . . . . . . .-2.0 v to v dd +2.0 v package po w er dissipation capability (t a = 25c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0 w s u rface mo u nt solder reflo w te m p e r a t u re . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260c for 10 seconds o u tp u t short circ u it c u rrent 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ma 1. o u tp u t shorted for no more than one second. n o more than one o u tp u t shorted at a time. table 5-1: operating range range ambient temp v dd commercial 0c to +70c 2.7-3.6 v industrial -40c to + 8 5c 2.7-3.6 v table 5-2: ac conditions of test 1 1. see fig u res 5-5 and 5-6 input rise/fall time output load 5ns c l = 30 pf table 5-3: dc operating characteristics symbol parameter limits test conditions min max units i ddr read current 10 ma ce#=0.1 v dd /0.9 v dd @25 mhz, so=open i ddr2 read current 15 ma ce#=0.1 v dd /0.9 v dd @50 mhz, so=open i ddr3 read current 20 ma ce#=0.1 v dd /0.9 v dd @50 mhz, so=open i ddw program and erase current 30 ma ce#=v dd i sb standby current 20 a ce#=v dd , v in =v dd or v ss i li input leakage current 1 a v in =gnd to v dd , v dd =v dd max i lo output leakage current 1 a v out =gnd to v dd , v dd =v dd max v il input low voltage 0. 8v v dd =v dd min v ih input high voltage 0.7 v dd v v dd =v dd max v ol output low voltage 0.2 v i ol =100 a, v dd =v dd min v ol2 output low voltage 0.4 v i ol =1.6 ma, v dd =v dd min v oh output high voltage v dd -0.2 v i oh =-100 a, v dd =v dd min downloaded from: http:///
SST25VF016B ds20005044c-page 20 ? 2015 microchip technology inc. table 5-4: capacitance (t a = 25c, f=1 mhz, other pins open) parameter description test condition maximum c out 1 output pin capacitance v out = 0 v 12 pf c in 1 input capacitance v i n = 0 v 6 pf 1. this parameter is meas u red only for initial q u alification and after a design or process change that co u ld affect this parameter. table 5-5: reliability characteristics symbol parameter minimum spec ification units test method n end 1 1. this parameter is meas u red only for initial q u alification and after a design or process change that co u ld affect this parameter. endurance 10,000 cycles jedec standard a117 t dr 1 data retention 100 years jedec standard a103 i lth 1 latch up 100 + i dd ma jedec standard 78 table 5-6: ac operating characteristics symbol parameter 25 mhz 50 mhz min max min max units f clk 1 1. maxim u m clock freq u ency for read instr u ction, 03h, is 25 mhz serial clock frequency 25 50 mhz t sckh serial clock high time 1 8 9n s t sckl serial clock low time 1 8 9n s t sckr 2 2. maxim u m rise and fall time may be limited by t sckh and t sckl req u irements serial clock rise time (slew rate) 0.1 0.1 v /ns t sckf serial clock fall time (slew rate) 0.1 0.1 v /ns t ces 3 3. relative to sck. ce# active setup time 10 5 ns t ceh 3 ce# active hold time 10 5 ns t chs 3 ce# not active setup time 10 5 ns t chh 3 ce# not active hold time 10 5 ns t cph ce# high time 100 50 ns t chz ce# high to high-z output 15 8 ns t clz sck low to low-z output 00n s t ds data in setup time 52n s t dh data in hold time 55n s t hls hold# low setup time 10 5 ns t hhs hold# high setup time 10 5 ns t hlh hold# low hold time 10 5 ns t hhh hold# high hold time 10 5 ns t hz hold# low to high-z output 20 8 ns t lz hold# high to low-z output 15 8 ns t oh output hold from sck change 00n s t v output valid from sck 15 8 ns t se sector-erase 25 25 ms t be block-erase 25 25 ms t sce chip-erase 50 50 ms t bp byte-program 10 10 s downloaded from: http:///
? 2015 microchip technology inc. ds20005044c-page 21 SST25VF016B figure 5-1: serial input timing diagram figure 5-2: serial output timing diagram figure 5-3: hold timing diagram high-z high-z ce# so si sck msb lsb t ds t dh t chh t ces t ceh t chs t sckr t sckf t cph 1271 serin.0 1271 sero u t.0 ce# si so sck msb t clz t v t sckh t chz t oh t sckl lsb t hz t lz t hhh t hls t hlh t hhs 1271 hold.0 hold# ce# sck so si downloaded from: http:///
SST25VF016B ds20005044c-page 22 ? 2015 microchip technology inc. 5.1 power-up specifications all functionalities and dc sp ecifications are specified for a v dd ramp rate of greater than 1v per 100 ms (0v - 3.0v in less than 300 ms). see table 5-7 and figure 5-4 for more information. figure 5-4: power-up timing diagram table 5-7: recommended system power-up timings symbol parameter minimum units t pu-read 1 1. this parameter is meas u red only for initial q u alification and after a design or process change that co u ld affect this parameter. v dd min to read operation 100 s t pu-write 1 v dd min to write operation 100 s time v dd min v dd max v dd de v ice fully accessi b le t pu-read t pu-write chip selection is not allowed. commands may not b e accepted or properly interpreted b y the de v ice. 1271 pwrup.0 downloaded from: http:///
? 2015 microchip technology inc. ds20005044c-page 23 SST25VF016B figure 5-5: ac input/output reference waveforms figure 5-6: a test load example 1271 ioref.0 reference points output input v ht v lt v ht v lt v iht v ilt ac test inputs are driven at v iht (0.9v dd ) for a logic 1 and v ilt (0.1v dd ) for a logic 0. measurement reference points for inputs and outputs are v ht (0.6v dd ) and v lt (0.4v dd ). input rise and fall times (10% ? 90%) are <5 ns. note: v ht - v high te s t v lt - v lo w te s t v iht - v i n put high test v ilt - v i n put lo w te s t 1271 tstld.0 to tester to dut c l downloaded from: http:///
SST25VF016B ds20005044c-page 24 ? 2015 microchip technology inc. 6.0 packaging diagrams for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: microchip technology drawing c04-14005a sheet 1 of 1 8-lead small outline integrated circui t (s2ae/f) - .208 inch body [soic] note: 1. all linear dimensions are in millimeters (max/min). 2. coplanarity: 0.1 mm 3. maximum allowable mold flash is 0.15 mm at the package ends and 0.25 mm between leads. downloaded from: http:///
? 2015 microchip technology inc. ds20005044c-page 25 SST25VF016B for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging note: microchip technology drawing c04-14008a sheet 1 of 1 8-lead very, very thin small outline no-leads (qae/f) - 5x6 mm body [wson] note: 1. all linear dimensions are in millimeters (max/min). 2. untoleranced dimensions (shown with box surround) are nominal target dimensions. 3. the external paddle is electrically connected to the die back-side and possibly to certain vss leads. this paddle can be soldered to the pc board; it is suggested to connect this paddle to the vss of the unit. connection of this paddle to any other voltage potential can result in shorts and/or electrical malfunction of the device. downloaded from: http:///
SST25VF016B ds20005044c-page 26 ? 2015 microchip technology inc. table 6-1: revision history revision description date 00 ? initial release of data sheet apr 2005 01 ? corrected ?jedec read-id? on page 17 incl u ding timing diagram ? corrected v ht and v lt val u es in fig u re 5-5 on page 23 sep 2005 02 ? migrated doc u ment to a data sheet ? updated s u rface mo u nt solder reflo w te m p e r a t u re information jan 2006 03 ? edited clock freq u ency speed from 50 mhz to 8 0 mhz in feat u res, page 1 ? revised table 5 for 8 0 mhz ? edited high speed read for 8 0 mhz, page 10 ? edited table 8 , page 21 ? added 8 0 mhz col u mns to table 12, page 22 ? updated prod u ct ordering information and v alid combination, page 26 sep 200 8 04 ? updated ?a u to address increment (aai) w ord-program?, ?end-of- w rite detection?, and ?hard w are end-of- w rite detection? on page 11 . ? revised fig u res 4- 8 and 4-9 on page page 12. ? updated doc u ment to ne w format. jan 2011 a ? added ?po w er-up specifications? on page 22 ? updated table 5-7 on page 22 ? released doc u ment u nder letter revision system ? updated spec n u mber from s71271 to ds25044 a u g 2011 b ? updated doc u ment to ne w corporate format ? eol of all 75 mhz parts. replacement parts are the 50 mhz parts fo u nd in this data sheet. jan 2015 c ? fixed an error in ?prod u ct identification system? on page 2 8 j u l 2015 downloaded from: http:///
? 2015 microchip technology inc. ds20005044c-page 27 SST25VF016B the microchip web site microchip provides online support via our www site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following informa- tion: product support C data sheets and errata, appli- cation notes and sample programs, design resources, users guides and hardware support documents, latest software releases and archived software general technical support C frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing business of microchip C product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of micro- chip sales offices, distributors and factory repre- sentatives customer change notification service microchips customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a spec- ified product family or development tool of interest. to register, access the microchip web site at www.microchip.com . under support, click on cus- tomer change notification and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: distributor or representative local sales office field application engineer (fae) technical support customers should contact their distributor, representa- tive or field application engineer (fae) for support local sales offices are also available to help custom- ers. a listing of sales offices and locations is included in the back of this document. technical support is available through the web site at: http://microchip.com/support downloaded from: http:///
SST25VF016B ds20005044c-page 28 ? 2015 microchip technology inc. 7.0 product iden tification system to order or obtain information, e.g., on pricing or deli very, refer to the factory or the listed sales office. part no. xx xx operating device device: SST25VF016B = 16 mbit, 2.7-3.6v, spi flash memory operating frequency: 50 = 50 mhz minimum endurance 4 = 10,000 cycles temperature: i = -40c to +85c c = 0c to +70c package: qaf/qae 1 = wson (6mm x 5mm body), 8-lead s2af/s2ae 1 = soic (200 mil body), 8-lead 1. s u ffix e = matte tin finish s u ffix f = n ickel plating w ith gold top (o u ter) layer finish tape and reel flag: t = tape and reel valid combinations: SST25VF016B-50-4c-s2af SST25VF016B-50-4c-s2af-t SST25VF016B-50-4i-s2af SST25VF016B-50-4i-s2af-t SST25VF016B-50-4i-s2ae SST25VF016B-50-4i-s2ae-t SST25VF016B-50-4c-qaf SST25VF016B-50-4c-qaf-t SST25VF016B-50-4i-qaf SST25VF016B-50-4i-qaf-t SST25VF016B-50-4i-qae SST25VF016B-50-4i-qae-t x tape/reel indicator frequency xx package temp C C C range minimum endurance C downloaded from: http:///
? 2015 microchip technology inc. ds20005044c-page 29 note the following details of the code protection feature on microchip devices: microchip products meet the specification cont ained in their particular microchip data sheet. microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. there are dishonest and possibly illegal meth ods used to breach the code protection fe ature. all of these methods, to our knowledge, require using the microchip products in a manner outside the operating specif ications contained in microchips data sheets. most likely, the person doing so is engaged in theft of intellectual property. microchip is willing to work with the customer who is concerned about the integrity of their code. neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as unbreakable. code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchips c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your softwa re or other copyrighted work, you may have a right to sue for relief under that act. quality management s ystem certified by dnv == iso/ts 16949 == information contained in this publication regarding device applications and the like is prov ided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application m eets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safe ty applications is entirely at the buyers risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or ot herwise, under any microchip intellectual property rights unless otherwise stated. trademarks the microchip name and logo, t he microchip logo, dspic, flashflex, flexpwr, jukeblox, k ee l oq , k ee l oq logo, kleer, lancheck, medialb, most, most logo, mplab, optolyzer, pic, picstart, pic 32 logo, righttouch, spynic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. the embedded control solutions company and mtouch are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, ecan, in-circuit serial programming, icsp, inter-chip connectivity, kleernet, kleernet logo, miwi, mpasm, mpf, mplab certified logo, mplib, mplink, multitrak, netdetach, omniscient code generation, picdem, picdem.net, pickit, pictail, righttouch logo, real ice, sqi, serial quad i/o, total endurance, tsharc, usbcheck, varisense, viewspan, wiperlock, wireless dna, and zena are trademarks of microchip technology incorpor ated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. gestic is a registered tradem ark of microchip technology germany ii gmbh & co. kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2015, microchip technology incorporated, printed in the u.s.a., 3 all rights reserved. isbn: 978-1-6277-622-8 microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the companys quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchips quality system for the design and manufacture of development systems is iso 9001:2000 certified. downloaded from: http:///
? 2015 microchip technology inc. ds20005044c-page 30 worldwide sales and service americas corporate office 2355 west chandler blvd. chandler, az 85224-6199 tel: 480-792-7200 fax: 480-792-7277 technical support: http://www.microchip.com/ support web address: www.microchip.com atlanta duluth, ga tel: 678-957-9614 fax: 678-957-1455 austin, tx tel: 512-257-3370 boston westborough, ma tel: 774-760-0087 fax: 774-760-0088 chicago itasca, il tel: 630-285-0071 fax: 630-285-0075 cleveland independence, oh tel: 216-447-0464 fax: 216-447-0643 dallas addison, tx tel: 972-818-7423 fax: 972-818-2924 detroit novi, mi tel: 248-848-4000 houston, tx tel: 281-894-5983 indianapolis noblesville, in tel: 317-773-8323 fax: 317-773-5453 los angeles mission viejo, ca tel: 949-462-9523 fax: 949-462-9608 new york, ny tel: 631-435-6000 san jose, ca tel: 408-735-9110 canada - toronto tel: 905-673-0699 fax: 905-673-6509 asia/pacific asia pacific office suites 3707-14, 37th floor tower 6, the gateway harbour city, kowloon hong kong tel: 852-2943-5100 fax: 852-2401-3431 australia - sydney tel: 61-2-9868-6733 fax: 61-2-9868-6755 china - beijing tel: 86-10-8569-7000 fax: 86-10-8528-2104 china - chengdu tel: 86-28-8665-5511 fax: 86-28-8665-7889 china - chongqing tel: 86-23-8980-9588 fax: 86-23-8980-9500 china - dongguan tel: 86-769-8702-9880 china - hangzhou tel: 86-571-8792-8115 fax: 86-571-8792-8116 china - hong kong sar tel: 852-2943-5100 fax: 852-2401-3431 china - nanjing tel: 86-25-8473-2460 fax: 86-25-8473-2470 china - qingdao tel: 86-532-8502-7355 fax: 86-532-8502-7205 china - shanghai tel: 86-21-5407-5533 fax: 86-21-5407-5066 china - shenyang tel: 86-24-2334-2829 fax: 86-24-2334-2393 china - shenzhen tel: 86-755-8864-2200 fax: 86-755-8203-1760 china - wuhan tel: 86-27-5980-5300 fax: 86-27-5980-5118 china - xian tel: 86-29-8833-7252 fax: 86-29-8833-7256 asia/pacific china - xiamen tel: 86-592-2388138 fax: 86-592-2388130 china - zhuhai tel: 86-756-3210040 fax: 86-756-3210049 india - bangalore tel: 91-80-3090-4444 fax: 91-80-3090-4123 india - new delhi tel: 91-11-4160-8631 fax: 91-11-4160-8632 india - pune tel: 91-20-3019-1500 japan - osaka tel: 81-6-6152-7160 fax: 81-6-6152-9310 japan - tokyo tel: 81-3-6880- 3770 fax: 81-3-6880-3771 korea - daegu tel: 82-53-744-4301 fax: 82-53-744-4302 korea - seoul tel: 82-2-554-7200 fax: 82-2-558-5932 or 82-2-558-5934 malaysia - kuala lumpur tel: 60-3-6201-9857 fax: 60-3-6201-9859 malaysia - penang tel: 60-4-227-8870 fax: 60-4-227-4068 philippines - manila tel: 63-2-634-9065 fax: 63-2-634-9069 singapore tel: 65-6334-8870 fax: 65-6334-8850 taiwan - hsin chu tel: 886-3-5778-366 fax: 886-3-5770-955 taiwan - kaohsiung tel: 886-7-213-7828 taiwan - taipei tel: 886-2-2508-8600 fax: 886-2-2508-0102 thailand - bangkok tel: 66-2-694-1351 fax: 66-2-694-1350 europe austria - wels tel: 43-7242-2244-39 fax: 43-7242-2244-393 denmark - copenhagen tel: 45-4450-2828 fax: 45-4485-2829 france - paris tel: 33-1-69-53-63-20 fax: 33-1-69-30-90-79 germany - dusseldorf tel: 49-2129-3766400 germany - karlsruhe tel: 49-721-625370 germany - munich tel: 49-89-627-144-0 fax: 49-89-627-144-44 italy - milan tel: 39-0331-742611 fax: 39-0331-466781 italy - venice tel: 39-049-7625286 netherlands - drunen tel: 31-416-690399 fax: 31-416-690340 poland - warsaw tel: 48-22-3325737 spain - madrid tel: 34-91-708-08-90 fax: 34-91-708-08-91 sweden - stockholm tel: 46-8-5090-4654 uk - wokingham tel: 44-118-921-5800 fax: 44-118-921-5820 07/14/15 downloaded from: http:///

▲Up To Search▲

Price & Availability of SST25VF016B

	To Download SST25VF016B Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .